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| as3930 single channel low frequency wakeup receiver www.ams.com/lf-receiver/as3930 revision 1.5 1 - 32 1 general description the as3930 is a single-c hannel low power ask re ceiver that is able to generate a wake-up upon detection of a data signal which uses a lf carrier frequency between 110 - 150 khz. the integrated correlator can be used for detection of a programmable 16-bit wake- up pattern. the as3930 provides a digital rssi value, it supports a programmable data rate. the as3930 offers a real-time clock (rtc), which is either derived from a crystal oscillator or the internal rc oscillator. the programmable features of as3930 enable to optimize its settings for achieving a longer distance while retaining a reliable wake-up generation. the sensitivity level of as3930 can be adjusted in presence of a strong field or in noisy environments. the device is available in a 16-pin tssop package. 2 key features ?? single channel ask wake-up receiver ?? carrier frequency range 110 - 150 khz ?? programmable wake-up pattern (16bits) ?? doubling of wake-up pattern supported ?? wake-up without pattern detection supported ?? wake-up sensitivity 100vrms (typ.) ?? adjustable sensitivity level ?? highly resistant to false wake-ups ?? false wake-up counter ?? periodical forced wake-up supported (1s ? 2h) ?? low power listening modes ?? current consumption in listening mode 1.37a (typ.) ?? programmable data-rate 0.5-4 kbaud (manchester encoded) ?? digital rssi ?? dynamic range 64db ?? 5-bit rssi step (2db per step) ?? rtc based on 32khz xtal, rc-osc, or external clock ?? operating temperature range -40oc to +85oc ?? operating supply voltage 2.4 - 3.6v (ta = 25oc) ?? bi-directional serial digital interface (sdi) ?? package options: 16-pin tssop and qfn 4x4 16 ld 3 applications the as3930 is ideal for active rfid tags, real-time location systems, operator identification, access control, and wireless sensors. vcc lf1p nc nc lfn vss gnd xin xout wake dat cs scl sdi sdo vcc cbat xtal cl tx transmitter as3930 transmitting antenna figure 1. as3930 typical application diagram with crystal oscillator
www.ams.com/lf-receiver/as3930 revision 1.5 2 - 32 as3930 datasheet - applications figure 2. as3930 typical application diagram without crystal oscillator figure 3. as3930 typical application diagram with clock from external source vcc lf1p nc nc lfn vss gnd xin xout wake dat cs scl sdi sdo vcc cbat tx transmitter as3930 transmitting antenna vcc lf1p nc nc lfn vss gnd xin xout wake dat cs scl sdi sdo vcc cbat tx transmitter as3930 transmitting antenna r c external clock www.ams.com/lf-receiver/as3930 revision 1.5 3 - 32 as3930 datasheet - contents contents 1 general description ............................................................................................................ ...................................................... 1 2 key features................................................................................................................... .......................................................... 1 3 applications................................................................................................................... ............................................................ 1 4 pin assignments ................................................................................................................ ....................................................... 4 4.1 16-pin tssop ................................................................................................................... ................................................................... 4 4.1.1 pin descriptions........................................................................................................ ................................................................... 4 4.2 qfn 4x4 16 ld.................................................................................................................. ................................................................... 5 4.2.1 pin descriptions........................................................................................................ ................................................................... 5 5 absolute maximum ratings ....................................................................................................... ............................................... 6 6 electrical characteristics..................................................................................................... ...................................................... 7 7 typical operating characteristics .............................................................................................. ............................................... 9 8 detailed description........................................................................................................... ..................................................... 10 8.1 operating modes ................................................................................................................ ................................................................ 11 8.1.1 power down mode ......................................................................................................... ........................................................... 11 8.1.2 listening mode .......................................................................................................... ................................................................ 11 8.1.3 preamble detection / pattern correlation ................................................................................ .................................................. 11 8.1.4 data receiving .......................................................................................................... ................................................................ 12 8.2 system and block specification ................................................................................................. ........................................................ 12 8.2.1 main logic and sdi ...................................................................................................... ............................................................. 12 8.2.2 serial data interface (sdi)............................................................................................. ............................................................ 14 8.2.3 sdi timing .............................................................................................................. ................................................................... 17 8.3 channel amplifier and frequency detector....................................................................................... ................................................. 18 8.3.1 frequency detector / agc ................................................................................................ ........................................................ 18 8.3.2 antenna damper.......................................................................................................... .............................................................. 19 8.4 demodulator / data slicer ...................................................................................................... ............................................................ 19 8.5 correlator..................................................................................................................... ....................................................................... 20 8.6 wake-up protocol - carrier frequency 125 khz................................................................................... .............................................. 22 8.6.1 without pattern detection............................................................................................... ........................................................... 22 8.6.2 single pattern detection ................................................................................................ ............................................................ 23 8.7 false wake-up register ......................................................................................................... ............................................................ 24 8.8 real time clock (rtc).......................................................................................................... ............................................................. 25 8.8.1 crystal oscillator...................................................................................................... .................................................................. 26 8.8.2 rc-oscillator ........................................................................................................... .................................................................. 26 8.8.3 external clock source ................................................................................................... ............................................................ 27 9 package drawings and markings .................................................................................................. ......................................... 28 10 ordering information........................................................................................................... .................................................. 31 www.ams.com/lf-receiver/as3930 revision 1.5 4 - 32 as3930 datasheet - pin assignments 4 pin assignments 4.1 16-pin tssop figure 4. tssop pin assignments (top view) 4.1.1 pin descriptions table 1. 16-pin tssop pin descriptions pin number pin name pin type description 1cs digital input chip select 2 scl sdi interface clock 3 sdi sdi data input 4 sdo digital output / tristate sdi data output (tristate when cs is low) 5v cc supply pad positive supply voltage 6 gnd negative supply voltage 7nc - not connected 8nc 9lf1p analog i/o input antenna 10 lfn antenna ground 11 xin crystal oscillator input 12 xout crystal oscillator output 13 v ss supply pad substrate 14 wake digital output wake-up output irq 15 dat data output 16 nc - not connected scl sdi sdo v cc gnd nc dat wake vss xout xin lfn cs nc nc lf1p 1 2 3 4 5 6 7 8 12 16 15 14 13 11 10 9 as3930 www.ams.com/lf-receiver/as3930 revision 1.5 5 - 32 as3930 datasheet - pin assignments 4.2 qfn 4x4 16 ld figure 5. qfn pin assignments (top view) 4.2.1 pin descriptions table 2. qfn 4x4 16 ld pin descriptions pin number pin name pin type description 1nc - not connected 2nc - 3lf1p analog i/o input antenna 4 lfn antenna ground 5 xin crystal oscillator input 6 xout crystal oscillator output 7v ss supply pad substrate 8 wake digital output wake-up output irq 9 dat data output 10 nc - not connected 11 cs digital input chip select 12 scl sdi interface clock 13 sdi sdi data input 14 sdo digital output / tristate sdi data output (tristate when cs is low) 15 v cc supply pad positive supply voltage 16 gnd negative supply voltage scl nc dat lf1p cs nc nc lfn 5 6 78 12 16 15 14 13 11 10 9 as3930a 1 2 3 4 wake vss xout xin sdi sdo v cc gnd www.ams.com/lf-receiver/as3930 revision 1.5 6 - 32 as3930 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 3 may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions beyond those indicated in electrical characteristics on page 7 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 3. absolute maximum ratings parameter min max units notes electrical parameters dc supply voltage (v dd )-0.55v input pin voltage (v in )-0.55v input current (latch up immunity) (i source ) -100 100 ma norm: jedec 78 electrostatic discharge electrostatic discharge (esd) 2 kv norm: mil 883 e method 3015 (hbm) continuous power dissipation total power dissipation (all supplies and outputs) (p t ) 0.07 mw temperature ranges and storage conditions storage temperature (t strg ) -65 150 oc package body temperature (t body ) 260 oc norm: ipc/jedec j-std-020 the reflow peak soldering temperature (body temperature) is specified according ipc/jedec j-std-020 ?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices?. humidity non-condensing 5 85 % moisture sensitivity level (msl) 3 represents a maximum floor time of 168h www.ams.com/lf-receiver/as3930 revision 1.5 7 - 32 as3930 datasheet - electrical characteristics 6 electrical characteristics table 4. electrical characteristics symbol parameter conditions min typ max units operating conditions v dd positive supply voltage 2.4 3.6 v v ss negative supply voltage 0 0 v t amb ambient temperature -40 85 oc dc/ac characteristics for digital inputs and outputs cmos input v ih high level input voltage 0.58*v dd 0.7*v dd 0.83* v dd v v il low level input voltage 0.125*v dd 0.2*v dd 0.3* v dd v i leak input leakage current 100 na cmos output v oh high level output voltage with a load current of 1ma v dd -0.4 v v ol low level output voltage v ss +0.4 v c l capacitive load for a clock frequency of 1 mhz 400 pf tristate cmos output v oh high level output voltage with a load current of 1ma v dd -0.4 v v ol low level output voltage v ss +0.4 v i oz tristate leakage current to v dd and v ss 100 na table 5. electrical system specifications symbol parameter conditions min typ max units input characteristics r in input impedance in case no antenna damper is set ( r1<4> =0) 2m fmin minimum input frequency 110 khz fmax maximum input frequency 150 khz current consumption ipwd power down mode 400 na ichrc current consumption in standard listening mode with channel active all the time and rc-oscillator as rtc 2.7 a ichoorc current consumption in on/off mode and rc-oscillator as rtc 11% duty cycle 1.37 a 50% duty cycle 2 ichxt current consumption in standard listening mode and crystal oscillator as rtc 3.5 5.9 a idata current consumption in preamble detection / pattern correlation / data receiving mode (rc-oscillator) with 125khz carrier frequency and 1kbps data-rate. no load on the output pins. 5.3 9 a www.ams.com/lf-receiver/as3930 revision 1.5 8 - 32 as3930 datasheet - electrical characteristics input sensitivity sens input sensitivity with 125khz carrier frequency, chip in default mode, 4 half bits burst + 4 symbols preamble and single preamble detection 100 vrms channel settling time tsamp amplifier settling time 250 s crystal oscillator fxtal frequency crystal dependent 32.768 khz txtal start-up time 1 s ixtal current consumption 1 a external clock source iextcl current consumption 1 a rc oscillator frcncal frequency if no calibration is performed 27 32.768 42 khz frccal32 if calibration with 32.768 khz reference signal is performed 31 32.768 34.5 khz frccalmax maximum achievable frequency after calibration 35 khz frccalmin minimum achievable frequency after calibration 30 khz tcalrc calibration time 65 periods of reference clock irc current consumption 200 na table 5. electrical system specifications symbol parameter conditions min typ max units www.ams.com/lf-receiver/as3930 revision 1.5 9 - 32 as3930 datasheet - typical operating characteristics 7 typical operating characteristics figure 6. sensitivity over voltage and temperature figure 7. sensitivity over rssi figure 8. rc-oscillator frequency over voltage (calibr.) figure 9. rc-oscillator frequency over temperature (calibr.) 1 10 100 1000 10000 100000 1000000 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 rssi [db] input voltage [vrms] 0 20 40 60 80 100 120 2.4 3 3.6 supply voltage [v] sensitivity [vrms] -40 o c 27 o c 95 o c 31 31.5 32 32.5 33 33.5 34 34.5 2.4 2.6 2.8 3 3.2 3.4 3.6 supply voltage [v] rc-osc frequency [khz] 31 31.5 32 32.5 33 33.5 34 34.5 -36-30-20-10 0 102030405060708090 operating temperature [ o c] rc-osc frequency [khz] www.ams.com/lf-receiver/as3930 revision 1.5 10 - 32 as3930 datasheet - detailed description 8 detailed description the as3930 is a one-dimensional low power low-frequency wake-up receiver. the as3930 is capable of detecting the presence of an inductive coupled carrier and extract the envelope of the on-off-keying (ook) modulated carrier. in case the carrier is manchester coded, then the clock is recovered from the transmitted signal and the data can be correlated with a programmed pattern. if the detected pattern corr esponds to the stored one, then a wake-up signal (irq) is risen up. the pattern correlation can be bypassed in which case the wake-up detectio n is based only on the frequency detection. the as3930 is made up of a single receiving channel, one envelop detector, one data correlator, 8 programmable registers with t he main logic and a real time clock. the digital logic can be accessed by an sdi. the real time clock can be based on a crystal oscillator or on an internal rc. if the internal rc oscillator is used, a calibration procedure can be performed to improve its accuracy. figure 10. block diagram of the lf wake-up receiver as3930 lf1p lfn gnd xin xout dat cs sdo sdi scl irq v cc rssi wakeup as3930, 1-d lf wakeup receiver sdi main logic envelope detector / data slicer correlator channel amplifier1 i/v bias xtal rtc rc rtc www.ams.com/lf-receiver/as3930 revision 1.5 11 - 32 as3930 datasheet - detailed description as3930 needs the following external components: ?? power supply capacitor ? cbat ? 100 nf ?? 32.768 khz crystal with its two pulling capacitors ? xtal and cl (it is possible to omit these components if the internal rc os cillator is used instead of the crystal oscillator) ?? input lc resonator in case the internal rc-oscillator is used (no crystal oscillator is mounted), the pin xin has to be connected to the supply, w hile pin xout should stay floating. application diagrams with and without crystal are shown in figure 1 and figure 2 . 8.1 operating modes 8.1.1 power down mode in power down mode, as3930 is completely switched off. the typical current consumption is 400 na. 8.1.2 listening mode in listening mode only the channel amplifier and the rtc are running. in this mode the system detects the presence of a carrier . in case the carrier is detected, the rssi can be displayed. in this mode it is possible to distinguish the following three sub modes: standard listening mode. the channel amplifier that is capable of detecting the presence of the carrier frequency, is active all the time. on/off mode (low power mode). the channel amplifier is active for one millisecond after which it is switched off. the off-time is programmable (see r4<7:6> ). figure 11. on/off mode further, for both sub modes, it is possible to enable a feature called artificial wake-up. if the artificial wake-up is enabled , then the as3930 produces an interrupt after a certain time regardless of whether any activity is detected on the input. the period of the artif icial wake-up is defined in the register r8<2:0> . the user can distinguish between artificial wake-up and wake-up based on the field detection (frequency or pattern detection) since the artificial wake-up interrupt lasts only 128s. with this interrupt the microcontroller ( c) can get feedback on the surrounding environment (e.g. read the false wake-up register r13<7:0> ) and/or take actions in order to change the setup. 8.1.3 preamble detection / pattern correlation the preamble detection and pattern correlation are only considered for the wake-up when the data correlator function is enabled . see r1<1> . the correlator searches first for preamble frequency (constant frequency of manchester clock defined according to bit-rate tran smission, see table 19 ) and then for data pattern. if the pattern is matched, then the wake-up interrupt is displayed on the wake output and the chip goes in data receiving mode. if the pattern fails, then the internal wake-up is terminated and no irq is produced. channel presence of carrier t0 t0 + 1ms t0 + t t0 + t + 1ms t0 + 2t time time www.ams.com/lf-receiver/as3930 revision 1.5 12 - 32 as3930 datasheet - detailed description 8.1.4 data receiving after a successful wake-up the chip enters the data receiving mode. in this mode, the chip can be retained as a normal ook rece iver. the received data are displayed on the dat pin. it is possible to put the chip back in to listening mode either with a direct comma nd (clear_wake, see table 12 ) or by using the timeout feature. this feature automatically sets the chip back to listening mode after a certain time defined in the r7<7:5> . 8.2 system and bl ock specification 8.2.1 main logic and sdi register table description and default values. table 6. register table 7 6 5 4 3 2 1 0 r0 n.a. on_off reserved en_a pwd r1 abs_hy agc_tlim agc_ud att_on n.a. en_pat2 en_wpat en_rtc r2 s_absh w_pat_t<1:0> reserved s_wu1<1:0> r3 hy_20m hy_pos fs_slc<2:0> fs_env<2:0> r4 t_off<1:0> r_val<1:0> gr<3:0> r5 ts2<7:0> r6 ts1<7:0> r7 t_out<2:0> t_hbit<4:0> r8 n.a. t_auto<2:0> r9 n.a. reserved r10 n.a. rssi1<4:0> r11 n.a. r12 n.a. r13 f_wake table 7. description and default values register name type default value description r0<5> on_off r/w 0 on/off operation mode. (duty-cycle defined in the register r4<7:6> ) r0<4> mux_123 r/w 0 reserved (it is not allowed to set this bit to 1) r0<3> reserved 1 reserved r0<2> reserved 1 reserved r0<1> en_a r/w 1 channel enable r0<0> pwd r/w 0 power down r1<7> abs_hy r/w 0 data slicer absolute reference r1<6> agc_tlim r/w 0 agc acting only on the first carrier burst r1<5> agc_ud r/w 1 agc operating in both directions (up-down) r1<4> att_on r/w 0 antenna damper enable r1<3> reserved 0 reserved r1<2> en_pat2 r/w 0 double wake-up pattern correlation r1<1> en_wpat r/w 1 data correlation enable r1<0> en_rtc r/w 1 crystal oscillator enable www.ams.com/lf-receiver/as3930 revision 1.5 13 - 32 as3930 datasheet - detailed description r2<7> s_absh r/w 0 data slicer threshold reduction r2<6:5> w_pat r/w 00 pattern correlation tolerance (see table 20) r2<4:2> reserved 000 reserved r2<1:0> s_wu1 r/w 00 tolerance setting for the stage wake-up (see table 14) r3<7> hy_20m r/w 0 data slicer hysteresis if hy_20m = 0, then comparator hysteresis = 40mv if hy_20m = 1, then comparator hysteresis = 20mv r3<6> hy_pos r/w 0 data slicer hysteresis on both edges (hy_pos=0 hysteresis on both edges; hy_pos=1 hysteresis only on positive edges) r3<5:3> fs_scl r/w 100 data slicer time constant (see table 18) r3<2:0> fs_env r/w 000 envelop detector time constant (see table 17) r4<7:6> t_off r/w 00 off time in on/off operation mode t_off=00 1ms t_off=01 2ms t_off=10 4ms t_off=11 8ms r4<5:4> d_res r/w 01 antenna damping resistor (see table 16) r4<3:0> gr r/w 0000 gain reduction (see table 15) r5<7:0> ts2 r/w 01101001 2 nd byte of wake-up pattern r6<7:0> ts1 r/w 10010110 1 st byte of wake-up pattern r7<7:5> t_out r/w 000 automatic time-out (see table 21) r7<4:0> t_hbit r/w 01011 bit rate definition (see table 19) r8<2:0> t_auto r/w 000 artificial wake-up t_auto=000 no artificial wake-up t_auto=001 1 sec t_auto=010 5 sec t_auto=011 20 sec t_auto=100 2 min t_auto=101 15 min t_auto=110 1 hour t_auto=111 2 hour r9<6:0> reserved 000000 reserved r10<4:0> rssi r rssi channel r11<4:0> rn.a. r12<4:0> rn.a. r13<7:0> f_wak r false wake-up register table 7. description and default values register name type default value description www.ams.com/lf-receiver/as3930 revision 1.5 14 - 32 as3930 datasheet - detailed description 8.2.2 serial data interface (sdi) this 4-wire interface is used by the microcontroller (c) to program the as3930. the maximum clock operation frequency of the s di is 2 mhz. note: sdo is set to tristate if cs is low. in this way mo re than one device can communicate on the same sdo bus. sdi command structure. to program the sdi, the cs signal has to go high. a sdi command is made up of two bytes serial command and the data is sampled on the falling edge of sclk. table 9 shows how the command looks like, from the msb (b15) to lsb (b0). the command stream has to be sent to the sdi from the msb (b15) to the lsb (b0). the first two bits (b15 and b14) define the operating mode. there are three modes available (write, read, direct command) plus one spare (not used), as shown in table 10 . in case a write or read command happens, then the next 6 bits (b13 to b8) define the register address which has to be written r espectively read, as shown in table 11 . table 8. serial data interface (sdi) pins name signal signal level description cs digital input with pull down cmos chip select sdi digital input with pull down cmos serial data input for writing registers, data to transmit and/ or writing addresses to select readable register sdo digital output cmos serial data output for received data or read value of selected registers sclk digital input with pull down cmos clock for serial data read and write table 9. sdi command structure mode register address / direct command register data b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 table 10. bits b15, b14 b15 b14 mode 00 write 0 1 read 1 0 not allowed 1 1 direct command table 11. bits b13-b8 b13 b12 b11 b10 b9 b8 read/write register 000000 r0 000001 r1 000010 r2 000011 r3 000100 r4 000101 r5 000110 r6 000111 r7 001000 r8 001001 r9 001010 r10 www.ams.com/lf-receiver/as3930 revision 1.5 15 - 32 as3930 datasheet - detailed description the last 8 bits are the data that has to be written respectively read. a cs toggle high-low-high terminates the command mode. if a direct command is sent (b15-b14=11), then the bits from b13 to b8 define the direct command while the last 8 bits are omit ted. table 12 shows all possible direct commands. all direct commands are explained below: - clear_wake : clears the wake state of the chip. in case the chip has woken up (wake pin is high), the chip is set back to listening mode. - reset_rssi : resets the rssi measurement. - trim_osc : starts the trimming procedure of the internal rc oscillator (see figure 20 ). - clear_false : resets the false wake-up register ( r13<7:0> =00). - preset_default : sets all registers in the default mode, as shown in figure 7 . note: in order to get the as3930 work properly after sending the preset_default direct command, it is mandatory to write r0<3> =0 and r0<2> =0. writing of data to addressable registers ( write mode) the sdi is sampled at the falling edge of sclk (as shown in the following diagrams). a cs toggling high-low-high indicates the end of the write command after register has been written. the following example shows a write command. figure 12. writing of a single byte (falling edge sampling) 001011 r11 001100 r12 001101 r13 table 12. list of direct commands command_mode b13 b12 b11 b10 b9 b8 clear_wake 0 0 0 0 0 0 reset_rssi 0 0 0 0 0 1 trim_osc 000010 clear_false 000011 preset_default 0 0 0 1 0 0 table 11. bits b13-b8 b13 b12 b11 b10 b9 b8 read/write register cs sclk sdi 0 0 a5 a4 a3 a2 a1 a0 d5 d4 d3 d2 d1 d0 d7 d6 x x sclk rising edge data is transfered from c sclk falling edge data is sampled data is moved to address a5-a0 cs falling edge signals end of write mode two leading zeros indicate write mode www.ams.com/lf-receiver/as3930 revision 1.5 16 - 32 as3930 datasheet - detailed description figure 13. writing of register data with auto-incrementing address reading of data from addressable registers (read mode). once the address has been sent through sdi, the data can be fed through the sdo pin out to the microcontroller. a cs low toggling high-low-high has to be performed after finishing the read mode session, in order to indicate the end of the read command and prepare the interface to the next command control byte. to transfer bytes from consecutive addresses, sdi master has to keep the cs signal high and the sclk clock has to be active as long as data need to be read. figure 14. reading of a single register byte cs sclk sdi 00 a 5 a 4 a 3 a 2 a 1 a 0 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 x x data is moved to address www.ams.com/lf-receiver/as3930 revision 1.5 17 - 32 as3930 datasheet - detailed description figure 15. send direct command byte 8.2.3 sdi timing figure 16. sdi timing diagram table 13. sdi timing parameters symbol parameter min typ max units tcsclk time cs to sampling data 500 ns tdclk time data to sampling data 300 ns thcl sclk high time 200 ns tclk sclk period 1 s tclkcs time sampling data to cs down 500 ns tcst cs toggling time 500 ns cs sclk sdi 1 1 c5 c4 c3 c2 c1 c0 x x sclk rising edge data is transfered from c sclk falling edge data is sampled cs falling edge signals the end of command mode two leading one indicate command mode cs spi scl thcl tcsclk t t t tclk tdclk tcst tclkcs sclk www.ams.com/lf-receiver/as3930 revision 1.5 18 - 32 as3930 datasheet - detailed description 8.3 channel amplifier and frequency detector the channel amplifier consists of a variable gain amplifier (vga), an automatic gain control, and a frequency detector. the lat ter detects the presence of a carrier. as soon as the carrier is detected the agc is enabled, the gain of the vga is reduced and set to the rig ht value and the rssi can be displayed. 8.3.1 frequency detector / agc the frequency detection uses the rtc as time base. in case the internal rc oscillator is used as rtc, it must be calibrated, bu t the calibration is guaranteed for a 32.768 khz crystal oscillator only. the frequency detection criteria can be tighter or more relaxed accordi ng to the setup described in r2<1:0> (see table 14) . the agc can operate in two modes: ?? agc down only ( r1<5> =0) ?? agc up and down ( r1<5> =1) as soon as the agc starts to operate, the gain in the vga is se t to maximum. if the agc down only mode is selected, the agc can only decrease the gain. since the rssi is directly derived from the vga gain, the system holds the rssi peak. when the agc up and down mode is selected, the rssi can follow the input signal strength variation in both directions. regardless which agc operation mode is used, the agc needs maximum 35 carrier periods to settle. the rssi is stored in the register r10<4:0> . both agc modes (only down or down and up) can also operate with time limitation. this option allows agc operation only in time slot of 256s following the internal wake-up. then the agc (rssi) is frozen till the wake-up or rssi reset occurs. the rssi is reset either with the direct command 'clear_wakeup' or 'reset_rssi'. the 'reset_rssi' command resets only the agc s etting but does not terminate wake-up condition. this means that if the si gnal is still present the new agc setting (rssi) will appear not later than 300s (35 lf carrier periods) after the command was received. the agc setting is reset if for duration of 3 manchester half symbols n o carrier is detected. if the wake-up irq is cleared the chip will go back to listening mode. in case the maximum amplification at the beginning is a drawback (e.g. in noisy environment) it is possible to set a smaller st arting gain on the amplifier (see table 15) . in this way it is possible to reduce the false frequency detection. table 14. tolerance settings for wake-up r2<1> r2<0> tolerance 00 relaxed 0 1 tighter (medium) 1 0 stringent 1 1 reserved table 15. bit setting of gain reduction r4<3> r4<2> r4<1> r4<0> gain reduction 0 0 0 0 no gain reduction 0 0 0 1 n.a. 0 0 1 0 or 1 n.a. 0100 or 1 -4db 0110 or 1 -8db 1 0 0 0 or 1 -12db 1 0 1 0 or 1 -16db 1 1 0 0 or 1 -20db 1 1 1 0 or 1 -24db www.ams.com/lf-receiver/as3930 revision 1.5 19 - 32 as3930 datasheet - detailed description 8.3.2 antenna damper the antenna damper allows the chip to deal with higher field strength, it is enabled by register r1<4> . it consists of shunt resistors which degrade the quality factor of the resonator by reducing the signal at the input of the amplifier. in this way the resonator see s a smaller parallel resistance (in the band of interest) which degrades its quality factor in order to increase the linear range of the channel amp lifier (the amplifier does not saturate in presence of bigger signals). table 16 shows the bit setup. 8.4 demodulator / data slicer the performance of the demodulator can be optimized according to bit rate and preamble length as described in table 17 and table 18 . if the bit rate gets higher, the time constant in the envelop detector must be set to a smaller value. this means that higher n oise is injected because of the wider band. the next table is a rough indication of how the envelop detector looks like for different bit rates. by using proper data slicer settings it is possible to improve the noise immunity paying the penalty of a longer preamble. in fact if the data slice r has a bigger time constant it is possible to reject more noise, but every time a transmission occurs, the data slicer need time to settle. this s ettling time will influence the length of the preamble. table 18 gives a correlation between data slicer setup and minimum required preamble length. note: these times are minimum required, but it is recommended to prolong the preamble. table 16. antenna damper bit setup r4<5> r4<4> shunt resistor (parallel to the resonator at 125 khz) 00 1 k 01 3 k 10 9 k 1 1 27 k table 17. bit setup for envelop detector for different symbol rates r3<2> r3<1> r3<0> symbol rate [manchester symbols/s] 0 0 0 4096 0 0 1 2184 0 1 0 1490 01 1 1130 1 0 0 910 1 0 1 762 1 1 0 655 1 1 1 512 table 18. bit setup for data slicer for different preamble length r3<5> r3<4> r3<3> minimum preamble length [ms] 00 0 0.8 00 1 1.15 01 0 1.55 01 1 1.9 10 0 2.3 10 1 2.65 11 0 3 11 1 3.5 www.ams.com/lf-receiver/as3930 revision 1.5 20 - 32 as3930 datasheet - detailed description the comparator of the data slicer can work only with positive or with symmetrical threshold r3<6> . in addition the threshold can be 20 or 40 mv r3<7> . in case the length of the preamble is an issue the data slicer can also work with an absolute threshold r1<7> . in this case the bits r3<2:0> would not influence the performance. it is even possible to reduce the absolute threshold in case the environment is not parti cularly noisy r2<7> . 8.5 correlator after frequency detection, the data correlation is only performed if the correlator is enabled ( r1<1> =1). the data correlation consists of checking the presence of a preamble (on/off modulated carrier) followed by a certain pattern. after the frequency detection the correlator waits 16 bits (see bit rate definition in table 19 ) and if no preamble is detected the chip is set back to listening mode and the false-wake-up register ( r13<7:0> ) is incremented by one. to get started with the pattern correlation the correlator needs to detect at least 4 bits of the preamble (on/off modulated ca rrier). the bit duration is defined in the register r7<4:0> (see table 19) as function of the real time clock (rtc) periods. table 19. bit rate setup r7<4> r7<3> r7<2> r7<1> r7<0> bit duration in rtc clock periods bit rate (bits/s) symbol rate (manchester symbols/s) 0 0 0 1 1 4 8192 4096 0 0 1 0 0 5 6552 3276 0 0 1 0 1 6 5460 2730 0 0 1 1 0 7 4680 2340 0 0 1 1 1 8 4096 2048 0 1 0 0 0 9 3640 1820 0 1 0 0 1 10 3276 1638 0 1 0 1 0 11 2978 1489 0 1 0 1 1 12 2730 1365 0 1 1 0 0 13 2520 1260 01101 14 2340 1170 0 1 1 1 0 15 2184 1092 0 1 1 1 1 16 2048 1024 10000 17 1926 963 10001 18 1820 910 10010 19 1724 862 10011 20 1638 819 10100 21 1560 780 10101 22 1488 744 10110 23 1424 712 10111 24 1364 682 11000 25 1310 655 11001 26 1260 630 11010 27 1212 606 1 1 0 1 1 28 1170 585 1 1 1 0 0 29 1128 564 11101 30 1092 546 www.ams.com/lf-receiver/as3930 revision 1.5 21 - 32 as3930 datasheet - detailed description if the preamble is detected correctly the correlator keeps searching for a data pattern. the duration of the preamble plus the pattern should not be longer than 40 bits (see bit rate definition in table 19 ). the data pattern can be defined by the user and consists of two bytes which are stored in the registers r5<7:0> and r6<7:0> . the two bytes define the pattern consisting of 16 half bit periods. this means the pattern and the bit period can be selected by the user. the only limitation is that the pattern (in combination with preamble) must obey manchester coding and timing. it must be noted that according to manchester coding a down-to-up bit transition represents a symbol "0", while a trans ition up-to-down represents a symbol "1". if the default code is used (96 [hex]) the binary code is (10 01 01 10 01 10 10 01). msb has to be tra nsmitted first. the user can also select ( r1<2> ) if single or double data pattern is used for wake-up. in case double pattern detection is set, the same pattern has to be repeated 2 times. additionally, it is possible to set the number of allowed missing zero bits (not symbols) in the received bitstream ( r2<6:5> ), as shown in the table 20 . if the pattern is matched, then the wake-up interrupt is displayed on the wake output. if the pattern detection fails, then the internal wake-up is terminated with no signal sent to mcu and the false wake-up regist er will be incremented ( r13<7:0> ). the wake-up state is terminated with the direct command ?clear_wake? (see table 12) . this command terminates the mcu activity. the termination can also be automatic in case there is no response from mcu. the time out for automatic termination is set in a reg ister r7<7:5> , as shown in the table 21 . 11110 31 1056 528 11111 32 1024 512 table 20. allowed pattern detection errors r2<6> r2<5> maximum allowed error in the pattern detection 0 0 no error allowed 0 1 1 missed zero 1 0 2 missed zeros 1 1 3 missed zeros table 21. timeout setup r7<7> r7<6> r7<5> timeout 000 0 sec 001 50 msec 010 100 msec 011 150 msec 100 200 msec 101 250 msec 110 300 msec 111 350 msec table 19. bit rate setup r7<4> r7<3> r7<2> r7<1> r7<0> bit duration in rtc clock periods bit rate (bits/s) symbol rate (manchester symbols/s) www.ams.com/lf-receiver/as3930 revision 1.5 22 - 32 as3930 datasheet - detailed description 8.6 wake-up protocol - carrier frequency 125 khz 8.6.1 without pattern detection figure 17. wake-up protocol overview without pattern detection (only carrier frequency detection) in case the data correlation is disabled ( r1<1> =0), the as3930 wakes up upon detection of the carrier frequency only, as shown in figure 17 . in order to ensure that as3930 wakes up, the carrier burst has to last longer than 550 s. there are two possibilities to set as39 30 back to listening mode: either the microcontroller sends the direct command clear_wake via sdi, or the time out option is used ( r7<7:5> ). in case the latter is chosen, then the as3930 is automatically set to listening mode after the time defined in t_out ( r7<7:5> ), counting starts at the low-to- high wake edge on the wake pin. carrier burst data carrier burst > 550 us wake clear_wake dat www.ams.com/lf-receiver/as3930 revision 1.5 23 - 32 as3930 datasheet - detailed description 8.6.2 single pattern detection figure 18 shows the wake-up protocol in case the pattern correlation is enabled ( r1<1> =1) for a 125 khz carrier frequency. the initial carrier burst has to be longer than 550 s and can last maximum 16 bits (see bit rate definition in table 19 ). if the on/off mode is used ( r1<5> =1), the minimum value of the maximum carrier burst duration is limited to 10 ms. this is summarized in table 22 . in case the carrier burst is too long the internal wake-up will be set back to low and the false wake-up counter ( r13<7:0> ) will be incremented by one. the carrier burst must be followed by a preamble (0101... modulated carrier with a bit duration defined in table 19 ) and the wake-up pattern stored in the registers r5<7:0> and r6<7:0> . the preamble must have at least 4 bits and the preamble duration together with the pattern should not be longer than 40 bits. if the wake-up pattern is correct the signal on the wake pin is set to high and the data tra nsmission can get started. to set the chip back to listening mode the direct command clear_wake, as well as the time out option ( r7<7:5> ) can be used. figure 18. wake-up protocol overview with single pattern detection table 22. preamble requirements in standard mode, scanning mode and on/off mode bit rate (bit/s) maximum duration of the carrier burst in standard mode and scanning mode (ms) maximum duration of the carrier burst in on/off mode (ms) 8192 1.95 10 6552 2.44 10 5460 2.93 10 4680 3.41 10 4096 3.90 10 3640 4.39 10 3276 4.88 10 2978 5.37 10 2730 5.86 10 carrier burst preamble pattern data wake clear_wake dat 1-bit preamble preamble > 4-bit duration preamble + pattern < 40-bit duration carrier burst>360 us carrier burst<16-bit duration www.ams.com/lf-receiver/as3930 revision 1.5 24 - 32 as3930 datasheet - detailed description 8.7 false wake-up register the wake-up strategy in the as3930 is based on 2 steps: 1. frequency detection: in this phase, the frequency of the received signal is checked. 2. pattern correlation: here the pattern is demodulated and checked whether it corresponds to the valid one. if there is a disturber or noise capable to overcome the first step (frequency detection) without producing a valid pattern, th en a false wake-up call happens.each time this event is recognized a counter is incremented by one and the respective counter value is stored in a memo ry cell (false wake-up register). thus, the microcontroller can periodically look at the false wake-up register, to get a feeling how noisy th e surrounding environment is and can then react accordingly (e.g. reducing the gain of the lna during frequency detection, set the as3930 tem porarily to power down etc.), as shown in the figure 19 . the false wake-up counter is a useful tool to quickly adapt the system to any changes in the noise environment and thus avoid false wake-up events. most wake-up receivers have to deal with environments that can rapidly change. by periodically monitoring the number of false w ake-up events it is possible to adapt the system setup to the actual characteristics of the environment and enables a better use of the full flexibility of as3930. 2520 6.34 10 2340 6.83 10 2184 7.32 10 2048 7.81 10 1926 8.30 10 1820 8.79 10 1724 9.28 10 1638 9.76 10 1560 10.25 10.25 1488 10.75 10.75 1424 11.23 11.23 1364 11.73 11.73 1310 12.21 12.21 1260 12.69 12.69 1212 13.20 13.20 1170 13.67 13.67 1128 14.18 14.18 1092 14.65 14.65 1056 15.15 15.15 1024 15.62 15.62 table 22. preamble requirements in standard mode, scanning mode and on/off mode bit rate (bit/s) maximum duration of the carrier burst in standard mode and scanning mode (ms) maximum duration of the carrier burst in on/off mode (ms) www.ams.com/lf-receiver/as3930 revision 1.5 25 - 32 as3930 datasheet - detailed description figure 19. concept of false wake-up register together with system 8.8 real time clock (rtc) the rtc can be based on a crystal oscillator ( r1<0> =1), the internal rc-oscillator ( r1<0> =0) or an external clock source ( r1<0> =1). the crystal has higher precision of the frequency but a higher current consumption and needs three external components (crystal plu s two capacitors). the rc-oscillator is completely integrated and can be calibrated if a reference signal is available for a very sho rt time to improve the frequency accuracy. the calibration gets started with the trim_osc direct command. since no non-volatile memory is available th e calibration must be done every time after the rco was turned off. the rco is turned off when the chip is in power down mode, a por happened , or the crystal oscillator is enabled. since the rtc defines the time base of the frequency detection, the selected frequency (frequenc y of the crystal oscillator or the reference frequency used for calibration of the rc oscillator) should be about one forth of the carrier frequ ency: f rtc ~ f car * 0.25 (eq 1) where: f car is the carrier frequency f rtc is the rtc frequency note: the third option for the rtc is the use of an external clock source, which must be applied directly to the xin pin (xout floati ng). frequency detector pattern correlator wakeup level 1 wakeup level 2 wake false wakeup register unsuccessful pattern correlation register setup microcontroller read false wakeup register change setup to minimize the false wakeup events www.ams.com/lf-receiver/as3930 revision 1.5 26 - 32 as3930 datasheet - detailed description 8.8.1 crystal oscillator 8.8.2 rc-oscillator to trim the rc-oscillator, set the chip select (cs) to high before sending the direct command trim_osc over sdi. then 65 digita l clock cycles of the reference clock (e.g. 32.768 khz) have to be sent on the clock bus (scl), as shown in figure 20 . after that the signal on the chip select (cs) has to be pulled down. the calibration is effective after the 65th reference clock edge and it will be stored in a volatile memory. in case the rc-osc illator is switched off or a power-on-reset happens (e.g. battery change), then the calibration has to be repeated. figure 20. rc-oscillator calibration via sdi table 23. characteristics of xtal parameter conditions min typ max units crystal accuracy (initial) overall accuracy 120 p.p.m. crystal motional resistance 60 k frequency 32.768 khz contribution of the oscillator to the frequency error 5 p.p.m start-up time crystal dependent 1 s duty cycle 45 50 55 % current consumption 1 a table 24. characteristics of rco parameter conditions min typ max units frequency if no calibration is performed 27 32.768 42 khz if calibration is performed 31 32.768 34.5 khz calibration time periods of reference clock 65 cycles current consumption 200 na cs sclk sdi x x 65 clock cycles 11 1 00 00 0 direct command trim_osc reference clock www.ams.com/lf-receiver/as3930 revision 1.5 27 - 32 as3930 datasheet - detailed description 8.8.3 external clock source to clock the as3930 with an external signal the crystal oscillator has to be enabled ( r1<0> =1). as shown in figure 3 , the clock must be applied on the pin xin while the pin xout must stay floating. the rc time constant has to be 100 s with a tolerance of 10% (e.g. r=680 k and c=22pf). in table 25 , the clock characteristics are summarized. note: in power down mode the external clock has to be set to v dd . table 25. characteristics of external clock symbol parameter min typ max units vi low level 0 0.1*v dd v vh high level 0.9*v dd v dd v tr rise-time 3 s tf fall-time 3 s t=1/2 rc rc time constant 90 100 110 s www.ams.com/lf-receiver/as3930 revision 1.5 28 - 32 as3930 datasheet - package drawings and markings 9 package drawings and markings the product is available in a 16-pin tssop and qfn 4x4 16 ld package. figure 21. 16-pin tssop package marking: yywwmzz. yy ww m zz @ year (i.e. 10 for 2010) manufacturing week assembly plant identifier assembly traceability code sublot identifier symbol min nom max a- -1.20 a1 0.05 - 0.15 a2 0.80 1.00 1.05 b0.19 - 0.30 c0.09 - 0.20 d 4.905.005.10 e - 6.40 bsc - e1 4.30 4.40 4.50 e - 0.65 bsc - l 0.450.600.75 l1 - 1.00 ref - symbol min nom max r0.09 - - r1 0.09 - - s0.20 - - 10o 8o 2-12 ref- 3-12 ref- aaa - 0.10 - bbb - 0.10 - ccc - 0.05 - ddd - 0.20 - n16 as3930 @ yywwmzz notes: 1. dimensioning & tolerancing conform to asme y14.5m-1994 . 2. all dimensions are in millimeters. angles are in degrees. www.ams.com/lf-receiver/as3930 revision 1.5 29 - 32 as3930 datasheet - package drawings and markings figure 22. qfn 4x4 16 ld package marking: yywwxzz. yy ww x zz @ year (i.e. 10 for 2010) manufacturing week assembly plant identifier assembly traceability code sublot identifier symbol min nom max a 0.80 0.90 1.00 a1 0 0.02 0.05 a3 - 0.20 ref - l 0.35 0.40 0.45 l1 0 - 0.15 b 0.25 0.30 0.35 d 4.00 bsc e 4.00 bsc e 0.65 bsc d2 2.60 2.70 2.80 e2 2.60 2.70 2.80 aaa - 0.15 - bbb - 0.10 - ccc - 0.10 - ddd - 0.05 - eee - 0.08 - fff - 0.10 - n16 notes: 1. dimensioning & tolerancing conform to asme y14.5m-1994 . 2. all dimensions are in millimeters. angles are in degrees. 3. dimension b applies to metallized terminal and is measured between 0.25mm and 0.30mm from terminal tip. dimension l1 represents terminal full back from package edge up to 0.15mm is acceptable. 4. coplanarity applies to the exposed heat slug as well as the terminal. 5. radius on terminal is optional. 6. n is the total number of terminals. as3930 @ yywwxzz www.ams.com/lf-receiver/as3930 revision 1.5 30 - 32 as3930 datasheet - revision history revision history note: typos may not be explicitly mentioned under revision history. revision date owner description 1.0 10 jul, 2009 rlc initial draft 1.2 08 apr, 2010 mrh updated the footer link, updated the figure title in figure 10 , added new information sdi timing 8.2.3 1.3 03 nov, 2010 rlc updated general description , key features , figure 1 , figure 2 , figure 3 , figure 11 , on/off mode (low power mode) , data receiving , table 7 , table 8 , revision history , ordering information , jedec standard in absolute maximum ratings . 08 dec, 2010 updated package drawings and markings and footnote in ordering information . 1.4 25 may, 2011 updated key features , package drawings and markings , ordering information . 08 jun, 2011 updated ipwd in table 5 ; registers r11, r12 in table 6 and table 7 . 1.5 04 feb, 2013 jry corrected data inconsistencies across the datasheet. www.ams.com/lf-receiver/as3930 revision 1.5 31 - 32 as3930 datasheet - ordering information 10 ordering information note: all products are rohs compliant and ams green. buy our products or get free samples online at www.ams.com/icdirect technical support is available at www.ams.com/technical-support for further information and requests, email us at sales@ams.com (or) find your local distributor at www.ams.com/distributor table 26. ordering information ordering code type marking delivery form 1 1. dry pack: moisture sensitivity level (msl) = 3, according to ipc/jedec j-std-033a. delivery quantity as3930-btst 16-pin tssop as3930 7 inches tape & reel 1000 pcs as3930-bqft qfn 4x4 16 ld as3930 7 inches tape & reel 1000 pcs www.ams.com/lf-receiver/as3930 revision 1.5 32 - 32 as3930 datasheet - copyrights copyrights copyright ? 1997-2013, ams ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registered ?. all right s reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written con sent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by ams ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. ams ag makes no warranty, express, statutory, implied, or by description rega rding the information set forth herein or regarding the freedom of the described devices from patent infringement. ams ag reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with ams ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliabi lity applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without addi tional processing by ams ag for each application. for shipments of less than 100 parts the manufacturing flow might show deviations from the stan dard production flow, such as test flow or test location. the information furnished here by ams ag is believed to be correct and accurate. however, ams ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruptio n of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, perfo rmance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of ams ag rendering of technical or other services. contact information headquarters ams ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel : +43 (0) 3136 500 0 fax : +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.ams.com/contact |
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